1. Field of Invention
The present invention relates to a method of fabricating an interlayer dielectric layer on a semiconductor substrate. More particularly, the present invention relates to a method for planarizing the interlayer dielectric layer on a semiconductor substrate.
2. Description of Related Art
In the structure of a semiconductor substrate with memory devices, such as dynamic random access memory (DRAM), the height variation between the memory cell region and periphery circuit region is big. The variation of height is caused by the enlargement of the surface of the bottom electrode at the memory cell for increasing the capacitance to a level sufficient to satisfy circuit demand. Therefore, the height of the bottom electrode causes the height variation between the memory cell region and periphery circuit region.
The big height variation between the memory cell region and the periphery circuit region will result in a poor pattern transfer for a metal interconnect in subsequent processing. Therefore, before fabricating the metal interconnect, the interlayer dielectric layer (ILD) should be planarized.
Conventionally, a planarized interlayer dielectric layer is fabricated by depositing boro-phosphosilicate glass (BPSG) with flowability on the surface of semiconductor devices and then chemical mechanical polishing (CMP) the BPSG layer. However, the planarized surface is only in the memory cell region or in the periphery circuit region, so the height variation between the memory cell region and the periphery circuit region is still significant.
FIGS. 1A to 1B schematically illustrate a conventional method for fabricating an interlayer dielectric layer on a semiconductor substrate. As shown in FIG. 1A, a semiconductor substrate 100 having a memory cell region 100a and a periphery circuit region 100b is provided. Semiconductor devices, such as capacitors or transistors have been formed on the semiconductor substrate. FIGS. 1A to 1B only show the height variation between the memory cell region 100a and the periphery circuit region 100b; the detailed arrangement of the semiconductor devices is not shown.
A silicon oxide layer 102 and boro-phosphosilicate glass (BPSG) layer 104 are deposited on the semiconductor substrate 100 by conventional chemical vapor deposition. The primary planarization on the memory cell region 100a and periphery circuit region 100b is provided by the flowability of the BPSG layer 104.
Referring to FIG. 1B, a chemical mechanical polishing (CMP) process is executed on the BPSG layer for further planarization of the same. Then, an oxide layer 106 is blanket-formed on BPSG layer 104 to cover up the damage thereon caused by CMP process. Therefore, a planarization of the interlayer dielectric layer is obtained only at the memory cell region 100a or the periphery circuit region 100b. However, the height variation between the memory cell region 100a and periphery circuit region 100b is still significant.
In addition, in the above-mentioned conventional method, the polishing of BPSG layer is controlled by the operation time. Therefore, it is not easy to control the polishing level of BPSG. Furthermore, due to the height difference between the memory cell region and the periphery circuit region on the semiconductor substrate, the polishing rate thereon is different so as to result in poor uniformity.